Conventionally, SRAMs and DRAMs (Dynamic Random Access Memory) have widely been used as rewritable semiconductor memories. SRAMs have mainly been used when high-speed operation is required, while DRAMs have been used when large storage capacity is required.
In DRAMs, since data signals read from memory cells are small, it is required to perform a series of operations including steps of: precharging/equalizing bit lines to a predetermined voltage before reading, driving word lines to connect the memory nodes of memory cells with bit lines; amplifying the small data signals appearing on the bit lines; turning bit switches on to read out data to the outside of the memory cell array, thereafter or simultaneously therewith, restoring data into the original memory cells, and precharging/equalizing the bit lines. In the case of writing too, it is required to perform substantially similar operations except that external write data are delivered to the bit lines before the restoration mentioned above. It is impossible to stop such a series of operations on the way, once the driving of word lines is started. This is because data is destructively read from the memory cells by driving word lines, regardless of whether the cycle is a read cycle or a write cycle.
In portable devices such as cellular phones, SRAMs have been widely used because they can be easily used and the necessary storage capacity is not so large, but recently, in order to support applications requiring large data capacity such as images or the like, pseudo SRAMs (PSRAM, VSRAM, or the like) have come to be used, which use the same dynamic memory cells as those of DRAMs adapted to provide a large storage capacity and in which the external interface and the external control method are the same or substantially same as those of SRAMs. Since pseudo SRAMs use the dynamic memory cells, they require the refresh operation. There are two types of pseudo SRAMs in terms of the refresh control; one requires external instructions to perform the refresh operation and the other does not require the same. As a matter of course, the type which does not require the instructions to perform the refresh operation is apparently superior in ease of use to the other, but since it is necessary to complete the refresh control within pseudo SRAMs, the configuration and the internal control in such pseudo SRAMs become complicated. In addition, the mainstream of the external interfaces of pseudo SRAMs is the same as that of the external interfaces of synchronous SRAMs. It is considered that designing the synchronous type SRAMs is easier than designing the asynchronous type SRAMs, since it is necessary to complete a series of operations as described above when the dynamic memory cells are used. However, pseudo SRAMs aiming at having interfaces similar to those of asynchronous SRAMs have recently begun to be proposed.
For example, Japanese Unexamined Patent Publication No. 2002-269977 discloses an asynchronous pseudo SRAM using dynamic memory cells. In this pseudo SRAM, transition of address signals is detected by an ATD (Address Transition Detection) circuit and an ATD signal is generated. The ATD signal is activated for a period required for accessing the memory cell array (for example, 100 nanoseconds). An internal circuit control signal is then generated on the basis of the ATD signal, and row-system circuits and column-system circuits are controlled. The reason why the activation period of the ATD signal, namely the internal circuit control signal, is prolonged is described herein “. . . because the read operation, for example, of the row-system circuits of the memory performs a series of operations including steps of: latching row addresses; selecting word lines on the basis of the addresses to read out data of the memory cells onto bit lines; and sense-amplifying minute potential generated on the bit lines by sense amplifiers to bring the potential of the bit lines to intended end potential levels . . . ” (see paragraph 0018 of the Publication No. 2002-269977).
Namely, this pseudo SRAM apparently performs asynchronous operation triggered by transition of the address signals, but when the address signals transit and the internal circuit control signal is once activated, no new access requests are accepted, and all of them are disregarded during the long activation period.
In addition, according to specifications of asynchronous SRAMs, it is allowed to activate the write enable signal /WE to perform a write request before elapse of a time required for access from activation of the chip enable signal /CE to a series of operations as described above, but the pseudo SRAM described in the Publication No. 2002-269977 does not satisfy even these specifications. Namely, since it is unpredictable, at the time the chip enable signal /CE is activated, whether or not the write enable signal /WE is activated, the pseudo SRAM has to start the read operation in preparation for the case that the write enable signal /WE would not be activated. This is because inactivation of the write enable signal /WE at the time the chip enable signal /CE is activated means a read request. Hence, once the read operation is started, it is impossible to receive any new access requests until a series of operations as described above are finished.
Japanese Unexamined Patent Publication No. 2003-308692 proposes measures to be taken in a case where the initial rise of the write enable signal /WE is late. Asynchronous SRAM imports write data with the rise of one of the write enable signal /WE and the chip enable signal /CE which is earlier than the other. According to the specifications of asynchronous SRAMs, it is assumed that there is no problem no matter how late the rising time of the write enable signal /WE from the start of the write cycle may be. Therefore, in order to deal with such a case, the pseudo SRAM according to the Publication No. 2003-308692 separately generates an internal circuit control signal in the case of write operations. However, as in the case of the pseudo SRAM according to the Publication No. 2002-269977, this pseudo SRAM can not deal with a write request by a falling edge of the write enable signal /WE after the chip enable signal /CE falls.
Japanese Patent No. 3170146 discloses a semiconductor memory which has realized a late write system, but, the system applies to synchronous SRAM, neither to asynchronous SRAM nor to asynchronous pseudo SRAM.
As described above, there are proposals for bringing the interface of pseudo SRAMs close to that of asynchronous SRAMs, but, no pseudo SRAMs which satisfy the specifications of asynchronous SRAMs and have compatibility with the same in operation as well have yet been realized.